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authorPeter Maydell <peter.maydell@linaro.org>2019-06-06 18:10:46 +0100
committerPeter Maydell <peter.maydell@linaro.org>2019-06-13 13:41:19 +0100
commit245f69ada691a5d1d90ec439be9d4bb5d5706ba6 (patch)
treed2dcd925a517f8a15f7d4b386f2fa423ab3a6693
parent22735abfc99240cb5bc614ee1ce688670a9599e2 (diff)
downloadrisu-245f69ada691a5d1d90ec439be9d4bb5d5706ba6.tar.gz
arm.risu: Add patterns for VFP<->gpreg transfers
Add instruction patterns to cover the "transfer between Arm core and extension register" spaces (A7.8 and A7.9 in DDI0406C.c). We omit VMSR/VMRS because they might have side effects (for stores to special regs) or give results dependent on previous execution (for loads). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190606171046.2732-1-peter.maydell@linaro.org
-rw-r--r--arm.risu33
1 files changed, 25 insertions, 8 deletions
diff --git a/arm.risu b/arm.risu
index af73345..9009e6b 100644
--- a/arm.risu
+++ b/arm.risu
@@ -111,11 +111,6 @@ SBC_imm A1 cond:4 0010110 s:1 rn:4 rd:4 imm:12
SBC_reg A1 cond:4 0000110 s:1 rn:4 rd:4 imm:5 type:2 0 rm:4
SBC_rsr A1 cond:4 0000110 s:1 rn:4 rd:4 rs:4 0 type:2 1 rm:4
-# vector duplicate (reg)
-# b:e == 11 UNDEF
-VDUP A1a cond:4 1110 1 b 1 0 vd:3 0 rt:4 1011 d 0 e 1 0000 { ($b == 0) || ($e == 0); }
-VDUP A1b cond:4 1110 1 b 0 0 vd:4 rt:4 1011 d 0 e 1 0000 { ($b == 0) || ($e == 0); }
-
########### Neon loads and stores #########################
# These patterns cover all the Neon element/structure
# load store insns, ie the whole of the space in section
@@ -707,9 +702,6 @@ VFNM A1 cond:4 11101 d 01 vn:4 vd:4 101 sz n op m 0 vm:4
########### Extension register load/store #################
# The following sets of patterns cover:
# 'extension register load/store insns' (A7.6)
-# Still TODO:
-# '8, 16 and 32 bit transfers' (A7.8)
-# '64 bit transfers (A7.9)
# as described in DDI0406B
###########################################################
@@ -775,6 +767,31 @@ VLDR A1a cond:4 1101 1 d 01 rn:4 vd:4 101 x imm:8 \
VLDR A1b cond:4 1101 1 d 01 rn:4 vd:4 101 x imm:8 \
!memory { reg_minus_imm($rn, $imm * 4); }
+########### Extension register transfer ###################
+# The following sets of patterns cover:
+# '8, 16 and 32-bit transfer between ARM core and
+# extension registers' (A7.8)
+# as described in DDI0406C
+# with the exception of VMSR/VMRS.
+###########################################################
+
+VMOV_core_single A1 cond:4 1110 000 op:1 vd:4 rt:4 1010 n:1 0010000
+VMOV_core_scalar A1 cond:4 1110 0 opc:2 0 vd:4 rt:4 1011 d:1 opc2:2 10000
+VMOV_scalar_core A1 cond:4 1110 u:1 opc:2 1 vn:4 rt:4 1011 n:1 opc2:2 10000
+
+# vector duplicate (reg)
+# b:e == 11 UNDEF
+VDUP A1a cond:4 1110 1 b 1 0 vd:3 0 rt:4 1011 d 0 e 1 0000 { ($b == 0) || ($e == 0); }
+VDUP A1b cond:4 1110 1 b 0 0 vd:4 rt:4 1011 d 0 e 1 0000 { ($b == 0) || ($e == 0); }
+
+########### Extension register transfer ###################
+# The following sets of patterns cover:
+# '64-bit transfers between ARM core and extension
+# registers' (A7.8)
+# as described in DDI0406C
+###########################################################
+VMOV_core_2single A1 cond:4 1100 010 op:1 rt2:4 rt:4 1010 00 m:1 1 vm:4 { ($vm != 0xf || $m != 1) && ($op == 0 || $rt2 != $rt); }
+VMOV_core_double A1 cond:4 1100 010 op:1 rt2:4 rt:4 1011 00 m:1 1 vm:4 { $op == 0 || $rt2 != $rt; }
#####
# v8 only insns