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This fixes the pattern for the Deliver A Random Number (darn)
instruction to ensure that the value of the L field, which is
used to determine the type and length of the generated random
number, is never 3 which is currently reserved for future use.
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Message-id: 20180906065146.2353-1-sandipan@linux.ibm.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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The pattern for the Load Quadword (lq) instruction is fixed.
If rtp is 0 or 12, the instruction will overwrite r0, r1 or
r12, r13 respectively. However, r1 is the stack frame pointer
and r13 is the thread pointer. So, overwriting them can cause
a crash. This is avoided by putting a constraint to prevent
rtp from being 0 or 12.
For a given effective address (ea), this instruction loads
two dwords from ea and ea+8. However, if ea is the start
address of the current stack frame, then the value of the
back chain dword from the previous stack frame, which is at
ea+8, is loaded on to one of the registers. This can cause
a mismatch as the addresses may vary across the master and
the apprentice instances. This is avoided by always adding
8 to the offset used for calculating the ea.
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Message-id: 20180306120813.17537-3-sandipan@linux.vnet.ibm.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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The patterns for the following instructions are added:
* Load Byte and Zero (lbz)
* Load Byte and Zero with Update (lbzu)
* Load Byte and Zero Indexed (lbzx)
* Load Byte and Zero with Update Indexed (lbzux)
* Load Doubleword (ld)
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Message-id: 20180306120813.17537-2-sandipan@linux.vnet.ibm.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Commit c10b97092 changed some field names in rldicr and rldimi patterns
but forgot to update the constraints to match the change. Since the
field (previously 'rb' and now 'sh') is an immediate rather than a
register number, the correct fix is to just delete the constraint
since we don't need to avoid particular values.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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The patterns for the following instructions are fixed:
* Rotate Left Doubleword then Clear Right (rldcr[.])
* Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
* Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])
The first instruction has a typo. For the other two instructions,
the extended opcodes are incorrect and the shift field 'sha' is
absent. Also, the shift field 'sh' should be used in place of the
register field 'rb'.
Signed-off-by: Sandipan Das <sandipandas1990@gmail.com>
Reviewed-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Message-id: 1495444679-7736-1-git-send-email-sandipandas1990@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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New constraint added to the referred instructions in order to avoid
generation of reserved (not used today) rounding modes for floating
point operations.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
Message-id: 1486174642-14883-2-git-send-email-joserz@linux.vnet.ibm.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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This file contains all PPC64 instructions found in ISAv3.0, book I.
Excepts traps, syscalls and jumps.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
Message-id: 1478452528-13684-10-git-send-email-joserz@linux.vnet.ibm.com
[PMM: fixed incorrect copyright line in ppc64.risu]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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