| Age | Commit message (Collapse) | Author |
|---|
|
We had an --sve switch, which would also enable sve,
but no way to turn sve off.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190206101446.6898-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
|
This is similar to the approach used by the FP/simd data in so far as
we generate a block of random data and then load into it. The loading
is actually done by the current vector length but that is implicit in
the run anyway.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180622141205.16306-8-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
|
The existing pattern support is useful but it does get a little
tedious when faced with large groups of instructions. This introduces
the concept of a @GroupName which can be sprinkled in the risu
definition and is attached to all instructions following its
definition until the next group or an empty group "@" is specified.
It can be combined with the existing pattern support to do things
like:
./risugen --group AdvSIMDAcrossVector --not-pattern ".*_RES" aarch64.risu foo.bin
Multiple groups will further restrict the set, so for example:
./risugen --group v8.2,Cryptographic aarch64.risu v8.2-crypto.bin
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180223154613.2096-2-alex.bennee@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
|
This moves the instruction selection to the common code and passes a
list of selection keys to write_test_code instead. This will allow us
to add selection features to the common code later.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20171031145444.13766-6-alex.bennee@linaro.org
|
|
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20170704144859.17644-7-alex.bennee@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
|
This commit adds an option to risugen in order to give the opportunity
to generated big-endian instructions. By passing --be, users force
risugen to generated big-endian instructions for ppc64.
./risugen --be --numinsns 1000 --pattern "ADD" ppc64.risu test.bin
./risugen --numinsns 1000 --pattern "ADD" ppc64.risu test.bin
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
Message-id: 1495739423-32326-4-git-send-email-joserz@linux.vnet.ibm.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
|
The progress bar functions are the same in every backend, so move
them to the common file.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
|
Create a new risugen_common module which we can use to store utility
functions that any CPU-specific backend might need to use.
Start it off with the implementations of open_bin(), close_bin(),
insn32() and insn16(), and remove those from the per-CPU files.
This requires us also to abstract out a way for the CPU backend
to specify whether it wants insn32 and insn16 to write big or
little endian values, so create one.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
|
This also fixes perl-mode's confusion about escaped strings.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20161209114830.9158-8-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
|
Use FindBin to ensure that we look for the per-CPU-arch
modules in the same directory as the script, rather than
assuming that:
(a) you ran risugen from the directory it was in
(b) "." is on the Perl @INC path
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
|
Instead of adding PPC64 in risugen, this commit removes ARM code
from risugen to make it more generic. Each arch will then implements
its own module that will be driven by this risugen.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
Message-id: 1478452528-13684-3-git-send-email-joserz@linux.vnet.ibm.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
|
Use 'sort keys %insn_details' rather than just 'keys %insn_details';
this doesn't affect correctness of the output, but does make it
deterministic from run to run.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
|
The correct logical operation to use for clearing bits in a register
is an AND, not an XOR. Correct the code we emit to align registers
to use the right logic op (and the right immediate value). The code
emitted to clear the NZCV flags had a similar problem but the fix
here is even simpler: just write the zero register to NZCV rather
than trying to do a read-mask-write.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
|
generate "interesting" values for aarch64 as well,
in the same way as we do for ARM.
Also disable use of LD1 to load 4 regs at a time, for now,
and replace with LDP Qn, which loads only 2 regs at a time.
As LD1 is implemented and stable, we can switch back to use it.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
|
|
The --pattern flag is useful for including whole classes of instructions.
You could also do specific instruction with it. However if you want a
whole class of instructions without a specific few instructions you'd
need to come up with a more complex regex.
With this you can for example to:
risugen --pattern ".* A64" --not-pattern "ROR.*" aarch64.risu test3.bin
|
|
This flag disables generation of floating point code
for initialization of the FP/SIMD registers, and
periodic randomization.
This does not of course prevent an input risu file
from generating floating point instructions.
This is useful to be able to test before FP support is available.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
|
|
aarch64 SIMD/fp instruction variants require addressing
in the form register plus register shifted by 4, to align
128bit data.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
|
|
use a global flag to control whether to re-randomize
registers periodically. This is useful for debugging purposes.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
|
|
initialize fpsr to 0 and fpcr to the user-supplied parameter
(default 0).
initialize and periodically update the V[] registers with
random floating point values.
Note that in contrast to arm we do not (yet) eskew the
random data for interesting values (NaN, 0, infinities, ..)
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
|
|
go back to store 8192 bytes of random data,
even though we actually use only the first 2K.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
|
|
addressing using pre-index / post-index and normal unscaled offset
only differ in encoding by a two bit-field.
Also there is no pre-index / post-index version of prefetch mem.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
|
|
new sextract function to extract a signed immediate from a field.
Used in aarch64.risu for ldnp / stnp first,
to implement the reg + 7bit signed offset immediate addressing.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
|
|
add ldnp and stnp.
Note that all loads and store suffer from the problem that
base register must be != target register.
This is in some cases a limitation of our framework
(in particular with stores),
in some cases it seems the Foundation models also do not
handle the case predictably (with loads).
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
|
|
non-functional change.
adds comments explaining problems, especially regarding load/stores.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
|
|
Eventually we will need to split the script into an
arch-independent part and an arch-dependent part
like the rest of the code.
Big thing to note is that this changes the length of the memory
block for loads and stores to the actual documented value of
~2K bytes of random data. Before, ~2K 32-bit words of random data
were written, for a total of ~8K. Not sure if this was intended,
but seems a bug, which gets fixed here.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
|
|
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
|
|
fix signal handling to work on aarch64.
We don't mess with SP, mainly.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
|
|
still float missing, test missing, yadda yadda.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
|
|
Avoid memory accesses escaping the data block by not generating
base addresses too close to either end.
|
|
|
|
|
|
Clean up our handling of ARM/Thumb switching by distinguishing between
"what mode are we in right now?" and "what mode does test code want to
be in?". Shuffle things around so write_test_code() is responsible for
doing all the prologue stuff, and write_random_register_data() is only
called explicitly, not implicitly by other things.
This makes it easy to make the actual bug fix, which is to call
write_random_register_data() after write_memblock_setup() so that
the latter doesn't have to clean its registers to not include any
address-location-dependent values.
|
|
|
|
Allow config files to specify a "memory" block; this effectively
enables the support for load/store insn tests which was implemented
in the preceding commits.
|
|
|
|
|
|
Add support for reg_plus_reg and reg_plus_reg_shifted
addressing modes.
|
|
Add the support code for setup and teardown of the memory
address for loads and stores with reg+imm addressing mode.
|
|
If any instruction specifies a 'memory' block, then set up a block
of random data and tell risu about it via the new SETMEMBLOCK op.
|
|
Generalise the routines for writing the magic UNDEF instructions which we
use to ask risu to do things for us, since we're going to be adding some
new risu ops for load/store handling.
|
|
Improve diagnostics for config files missing line continuation characters
by enforcing C-identifier rules for what is a valid instruction and
encoding name (alphanumerics plus underscore, must not start with digit).
|
|
|
|
Force blocks in risu config files to be at the ends of lines. Allow
them to be named (with an unnamed block being a constraints block
for backwards compatibility). At the moment the only recognised
block is "constraints".
|
|
Rework risugen's parser to use Text::Balanced; this opens the way
for a generalisation of the format to labelled brace-marked blocks,
so we can specify load/store memory usage as well as constraints.
|
|
|
|
|
|
Document the .risu file format in the README, rather than in
three duplicate comments in risugen, arm.risu and thumb.risu.
|
|
Add support to risugen for reading "directives" from the .risu
config file as well as instruction patterns. Use this to allow
the .risu file to specify whether it contains ARM mode or Thumb
mode patterns, rather than forcing the risugen user to pass the
correct command line argument for the .risu file being used.
|
|
|
|
Allow the name of a variable field in a pattern to include digits
(although it may not start with a digit).
|
