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2020-10-01arm.risu: Add patterns for fp16 insnsPeter Maydell
Add patterns for the fp16 half-precision floating point extension. Where older pre-fp16 patterns used to include UNDEF encodings that now mean fp16, constrain them so that tests generated from those patterns will give the same results on CPUs both with and without fp16. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-10-01arm.risu: Fix typo in VCVT_B_TT pattern namePeter Maydell
Fix typo in VCVT_B_TT pattern name. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2020-06-22arm.risu: Correct VLDR/VSTR U=0 patternsPeter Maydell
Correct the VLDR and VSTR patterns, which claimed to be setting U=0 but in fact left it identical to the U=1 pattern due to a cut-and-paste error. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2020-06-05arm.risu, thumb.risu: Add v8.2 DP and FHM insnsPeter Maydell
Add coverage for the v8.2 DP and v8.2 FHM insns in the Neon extension space. (We already had the v8.1 VQRDMLAH/VQRDLSH and the v8.3 VCADD/VCMLA, so this brings the risu coverage into line with what QEMU has implemented so far.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-02-24aarch64.risu: Add patterns for v8.3-RCPC and v8.4-RCPC insnsPeter Maydell
Add patterns for the new instructions in the v8.3-RCPC and v8.4-RCPC extensions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-17arm.risu: Avoid VTRN with Vd == VmPeter Maydell
The AArch32 VTRN instruction is specified to give an UNKNOWN result if Vd and Vm are the same register; avoid generating this in risu output, as we already do for VUZP and VZIP. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190613143741.15128-1-peter.maydell@linaro.org
2019-06-13arm.risu: Add patterns for VFP<->gpreg transfersPeter Maydell
Add instruction patterns to cover the "transfer between Arm core and extension register" spaces (A7.8 and A7.9 in DDI0406C.c). We omit VMSR/VMRS because they might have side effects (for stores to special regs) or give results dependent on previous execution (for loads). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190606171046.2732-1-peter.maydell@linaro.org
2019-06-13risu: Include <sys/user.h> on ppc64Peter Maydell
To build the C parts of risu for ppc64le with recent glibc/kernel headers, we need to include sys/user.h to avoid a compile error, because sys/ucontext.h defines a struct which includes a pointer to 'struct pt_regs' but does not provide a definition of that struct. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Sandipan Das <sandipan@linux.ibm.com> Message-id: 20190607132521.9637-1-peter.maydell@linaro.org
2019-06-07build-all-arches: include x86 triplets in the buildAlex Bennée
There are a couple of minor warts: - 32 bit x86 can be either i386-linux-gnu or i686-linux-gnu - skip looking for x86_64-linux-gnu-gcc in docker cross envs Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-07risu_reginfo_i386: rework --xfeatures value parsingJan Bobek
Have the --xfeatures option accept "sse", "avx" and "avx512" in addition to a plain numerical value, purely for users' convenience. Don't fail silently when an incorrect value is specified, to avoid confusion. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Jan Bobek <jan.bobek@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-07risu_reginfo_i386: replace xfeature constants with symbolic namesJan Bobek
The original code used "magic numbers", which made it unclear in some places. Include a reference to the Intel manual where the constants' meaning is discussed. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Jan Bobek <jan.bobek@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-07i386: Add avx512 state to reginfo_tRichard Henderson
The state expected for a given test must be specifically requested with the --xfeatures=mask command-line argument. This is recorded with the saved state so that it is obvious if the apprentice is given a different argument. Any features beyond what are present on the running cpu will read as zero. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-07configure: add i386/x86_64 architecturesJan Bobek
Now that i386 and x86_64 architectures are supported by RISU, we want to detect them and build RISU for them automatically. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Jan Bobek <jan.bobek@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-07test_i386: change syntax from nasm to gasJan Bobek
This allows us to drop dependency on NASM and build the test image with GCC only. Adds support for x86_64, too. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Jan Bobek <jan.bobek@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-07risu_i386: remove old unused codeJan Bobek
The code being removed is a remnant of the past implementation; it has since been replaced by its more powerful, architecture-independent counterpart in reginfo.c. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Jan Bobek <jan.bobek@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-07risu_i386: implement missing CPU-specific functionsJan Bobek
risu_i386.c is expected to implement the following functions: - advance_pc - get_reginfo_paramreg, set_ucontext_paramreg - get_risuop - get_pc This patch adds the necessary code. We use EAX as the parameter register and opcode "UD1 %xxx,%eax" for triggering RISU actions. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Jan Bobek <jan.bobek@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-07risu_reginfo_i386: implement arch-specific reginfo interfaceJan Bobek
CPU-specific code in risu_reginfo_* is expected to define and export the following symbols: - arch_long_opts, arch_extra_help, process_arch_opt - reginfo_size - reginfo_init - reginfo_is_eq - reginfo_dump, reginfo_dump_mismatch Make risu_reginfo_i386.c implement this interface; and while we're at it, expand the support to x86_64 as well. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Jan Bobek <jan.bobek@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-07risu_i386: move reginfo-related code to risu_reginfo_i386.cJan Bobek
In order to build risu successfully for i386, we need files risu_reginfo_i386.{h,c}; this patch adds the latter by extracting the relevant code from risu_i386.c. This patch is pure code motion; no functional changes were made. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Jan Bobek <jan.bobek@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-07risu_i386: move reginfo_t and related defines to risu_reginfo_i386.hJan Bobek
In order to build risu successfully for i386, we need files risu_reginfo_i386.{h,c}; this patch adds the former by extracting the relevant code from risu_i386.c. This patch is pure code motion; no functional changes were made. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Jan Bobek <jan.bobek@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-07Makefile: undefine the arch name symbolJan Bobek
At least GCC defines the symbol "i386" to 1 to signal the target platform. We need to use "i386" as an undefined symbol in order to correctly include risu_reginfo_i386.h from risu.h. Add an -U option to the build command to make sure the symbol remains undefined. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Jan Bobek <jan.bobek@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-08risugen: Default to sve offRichard Henderson
We had an --sve switch, which would also enable sve, but no way to turn sve off. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190206101446.6898-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-08aarch64: Fill in fp regs for test_aarch64.sRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190206101446.6898-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25ppc64.risu: Fix pattern for darnSandipan Das
This fixes the pattern for the Deliver A Random Number (darn) instruction to ensure that the value of the L field, which is used to determine the type and length of the generated random number, is never 3 which is currently reserved for future use. Signed-off-by: Sandipan Das <sandipan@linux.ibm.com> Message-id: 20180906065146.2353-1-sandipan@linux.ibm.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02risu_reginfo_aarch64: handle variable VQAlex Bennée
This involves parsing the command line parameter and calling the kernel to set the VQ limit. We also add dumping of the register state in the main register dump. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180622141205.16306-23-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02risu_reginfo_aarch64: limit SVE_VQ_MAX to current architectureRichard Henderson
The kernel headers optimistically assume it's going to grow but as we are never going to use that many on current hardware we limit SVE_VQ_MAX to what we will. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180622141205.16306-22-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02risu_reginfo_aarch64: add SVE support to reginfo_dump_mismatchAlex Bennée
We also tweak the justification of the rest of the registers so the : lines up nicely across the register dump and diff dump. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180622141205.16306-21-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02risu_reginfo_aarch64: add support for copying SVE register stateAlex Bennée
Add the ability to save SVE registers from the signal context. This is controlled with an optional flag --test-sve. The whole thing is conditionally compiled when SVE support is in the sigcontext headers. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180622141205.16306-20-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02risu_reginfo_aarch64: left justify regnums and drop masksAlex Bennée
Left justification is more pleasing to the eye than the default. We also drop the masking which isn't needed as we are casting to a smaller size anyway. This was split out of Richard's re-factoring work for SVE. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180622141205.16306-19-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02risu_reginfo: introduce reginfo_size()Alex Bennée
In preparation for conditionally supporting SVE we need to be able to have different sized reginfos. This introduces reginfo_size() to abstract the size away to the code the actually knows. For aarch64 we also use this while initialising the block. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180622141205.16306-18-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02risu_reginfo_aarch64: unionify VFP regsAlex Bennée
This is preparation for the SVE work as we won't want to be carrying around both VFP and SVE registers at the same time as they overlap. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180622141205.16306-17-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02risu_reginfo_aarch64: drop stray ;Alex Bennée
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180622141205.16306-16-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02risu: add process_arch_optRichard Henderson
Allows the backend to do more that just set a flag when it comes to processing options. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180622141205.16306-15-alex.bennee@linaro.org [AJB: tweaked order, added stdlib includes] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02risu: move optional args to each architectureAlex Bennée
The key variables here are: *arch_long_opts and *arch_extra_help. If they are not NULL then we concatenate the extra options to appropriate structure to enable the support. Adding architecture short options is not supported. This also includes moving the ARM specific test_fp_exc/test-fp-exc into ARM specific code. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180622141205.16306-14-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02contrib/generate_all.sh: allow passing of arguments to risugenAlex Bennée
This allows us to use any new risugen options when generating all our test patterns. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180622141205.16306-13-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02risugen: add dtype_msz address helperRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180622141205.16306-12-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02risugen: add reg_plus_imm_pl and reg_plus_imm_vl address helpersRichard Henderson
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180622141205.16306-11-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02risugen: use fewer insns for aarch64 immediate loadRichard Henderson
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180622141205.16306-10-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02risugen: Initialize sve predicates with random dataRichard Henderson
Using ptrue makes most of the uses of predicates trivial. Therefore, initialize them to something interesting. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180622141205.16306-9-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02risugen: add --sve supportAlex Bennée
This is similar to the approach used by the FP/simd data in so far as we generate a block of random data and then load into it. The loading is actually done by the current vector length but that is implicit in the run anyway. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180622141205.16306-8-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02Makefile: include risu_reginfo_$(ARCH) in HDRSAlex Bennée
Otherwise changes to reginfo don't cause the whole thing to be re-built causing much confusion when bisecting. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180622141205.16306-7-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02risu: add zlib indication to help textAlex Bennée
This is a simple aide-memoir as it can be tricky to determine this with a simple statically compiled binary. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180622141205.16306-6-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02build-all-arches: do a distclean $(SRC) configuredAlex Bennée
This can cause much confusion when you have been building in your source tree. I've added a distclean so we don't unexpectedly drop the config for normal make clean invocations. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180622141205.16306-5-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02build-all-arches: expand the range of docker imagesAlex Bennée
We won't actually want power, we want ppc64el for the 64 bit version. Also we will soon have m68k so include that as well. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180622141205.16306-4-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02comms: include header for writevAlex Bennée
The compiler complains about implicit declarations otherwise. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180622141205.16306-3-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02risu_reginfo_aarch64: include signal.h for FPSIMD_MAGICAlex Bennée
Building with the Bionic Beaver cross compilers fails which probably means we were getting this as a side effect before. Include the correct header to get at these bits. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180622141205.16306-2-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-06risu_reginfo_ppc64.c: Fix register name prefixSandipan Das
Use 'f' instead of 'r' as the prefix when dumping the values of floating-point registers. Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com> Message-id: 20180306120813.17537-4-sandipan@linux.vnet.ibm.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-06ppc64.risu: Fix pattern for load qwordSandipan Das
The pattern for the Load Quadword (lq) instruction is fixed. If rtp is 0 or 12, the instruction will overwrite r0, r1 or r12, r13 respectively. However, r1 is the stack frame pointer and r13 is the thread pointer. So, overwriting them can cause a crash. This is avoided by putting a constraint to prevent rtp from being 0 or 12. For a given effective address (ea), this instruction loads two dwords from ea and ea+8. However, if ea is the start address of the current stack frame, then the value of the back chain dword from the previous stack frame, which is at ea+8, is loaded on to one of the registers. This can cause a mismatch as the addresses may vary across the master and the apprentice instances. This is avoided by always adding 8 to the offset used for calculating the ea. Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com> Message-id: 20180306120813.17537-3-sandipan@linux.vnet.ibm.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-06ppc64.risu: Add missing byte and dword loadsSandipan Das
The patterns for the following instructions are added: * Load Byte and Zero (lbz) * Load Byte and Zero with Update (lbzu) * Load Byte and Zero Indexed (lbzx) * Load Byte and Zero with Update Indexed (lbzux) * Load Doubleword (ld) Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com> Message-id: 20180306120813.17537-2-sandipan@linux.vnet.ibm.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01Add arm and thumb vqrdml[as]h, vcadd, vcmlaRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01Add aa64 fcadd + fcmlaRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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