| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2020-10-01 | arm.risu: Add patterns for fp16 insns | Peter Maydell | |
| Add patterns for the fp16 half-precision floating point extension. Where older pre-fp16 patterns used to include UNDEF encodings that now mean fp16, constrain them so that tests generated from those patterns will give the same results on CPUs both with and without fp16. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | |||
| 2020-10-01 | arm.risu: Fix typo in VCVT_B_TT pattern name | Peter Maydell | |
| Fix typo in VCVT_B_TT pattern name. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | |||
| 2020-06-22 | arm.risu: Correct VLDR/VSTR U=0 patterns | Peter Maydell | |
| Correct the VLDR and VSTR patterns, which claimed to be setting U=0 but in fact left it identical to the U=1 pattern due to a cut-and-paste error. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | |||
| 2020-06-05 | arm.risu, thumb.risu: Add v8.2 DP and FHM insns | Peter Maydell | |
| Add coverage for the v8.2 DP and v8.2 FHM insns in the Neon extension space. (We already had the v8.1 VQRDMLAH/VQRDLSH and the v8.3 VCADD/VCMLA, so this brings the risu coverage into line with what QEMU has implemented so far.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | |||
| 2019-06-17 | arm.risu: Avoid VTRN with Vd == Vm | Peter Maydell | |
| The AArch32 VTRN instruction is specified to give an UNKNOWN result if Vd and Vm are the same register; avoid generating this in risu output, as we already do for VUZP and VZIP. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190613143741.15128-1-peter.maydell@linaro.org | |||
| 2019-06-13 | arm.risu: Add patterns for VFP<->gpreg transfers | Peter Maydell | |
| Add instruction patterns to cover the "transfer between Arm core and extension register" spaces (A7.8 and A7.9 in DDI0406C.c). We omit VMSR/VMRS because they might have side effects (for stores to special regs) or give results dependent on previous execution (for loads). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190606171046.2732-1-peter.maydell@linaro.org | |||
| 2018-03-01 | Add arm and thumb vqrdml[as]h, vcadd, vcmla | Richard Henderson | |
| Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | |||
| 2016-11-07 | Change mode directive of ARM risu files | Jose Ricardo Ziviani | |
| If different risufiles are managed by a single risugen (like thumb.risu, aarch64.risu, and arm.risu are managed by risugen_arm.pm) the mode directive identifies such operation by prepending the module name: thumb.risu - .mode arm.thumb aarch64.risu = .mode arm.aarch64 arm.risu = .mode arm Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Message-id: 1478452528-13684-4-git-send-email-joserz@linux.vnet.ibm.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | |||
| 2014-09-08 | Add crypto extension patterns | Peter Maydell | |
| Add patterns for the ARMv8 crypto extensions to the ARM and AArch64 risu files. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | |||
| 2014-04-25 | arm.risu: Patterns for ADC/SBC | Peter Maydell | |
| 2014-04-25 | arm.risu, thumb.risu: Patterns for new v8 insns | Peter Maydell | |
| 2011-11-14 | arm.risu: Add patterns for A15 insnns (fused mac, integer div) | Peter Maydell | |
| 2011-06-20 | arm.risu: Add patterns for VLDM, VSTR and VLDR. | Peter Maydell | |
| 2011-06-20 | arm.risu: Add patterns for VSTM | Peter Maydell | |
| 2011-05-06 | arm.risu: add pattern for REVSH | Peter Maydell | |
| 2011-05-06 | arm.risu: add patterns covering VFP data processing space | Peter Maydell | |
| 2011-04-11 | arm.risu: Remove obsolete patterns | Peter Maydell | |
| Remove some obsolete patterns than are now duplicated by the systematic coverage of neon data-processing insn space. | |||
| 2011-04-11 | arm.risu: Add patterns for the 'not in other category' Neon insns | Peter Maydell | |
| 2011-04-11 | arm.risu: add patterns for Neon "2 register misc" forms | Peter Maydell | |
| 2011-04-11 | arm.risu: Add patterns for the Neon 2reg+scalar forms | Peter Maydell | |
| 2011-04-11 | arm.risu: Add patterns for Neon "3 regs different lengths" insns | Peter Maydell | |
| 2011-04-11 | arm.risu: add patterns for Neon "2 regs + shift" | Peter Maydell | |
| 2011-04-11 | arm.risu: Add pattern for Neon "1 reg + modified immediate" forms | Peter Maydell | |
| 2011-04-11 | arm.risu: Add patterns covering all of Neon "3 reg same size" space | Peter Maydell | |
| 2011-04-11 | Add a few extra ARM insn patterns. | Peter Maydell | |
| 2011-03-24 | Add patterns for VST* multiple structures. | Peter Maydell | |
| Add patterns for VST* multiple structures. This completes the coverage of the neon element load/store space. | |||
| 2011-03-24 | Add patterns for VLD* "multiple structures" forms | Peter Maydell | |
| 2011-03-24 | Add ARM patterns for Neon "single element from one lane" stores. | Peter Maydell | |
| 2011-03-24 | Fix a silly error in the name of a couple of the VLD stoa patterns. | Peter Maydell | |
| 2011-03-24 | Add ARM patterns for VLD* single-element-to-one-lane | Peter Maydell | |
| 2011-03-15 | Add patterns for NEON VLD "one element to all lanes" loads | Peter Maydell | |
| 2011-03-14 | Add patterns for VMAX, VMIN and VRECPS | Peter Maydell | |
| 2011-03-11 | Add patterns for VDUP and various Neon float ops | Peter Maydell | |
| 2011-03-11 | Add patterns for dual multiplies | Peter Maydell | |
| 2011-03-10 | Add patterns for non-saturating parallel add/sub | Peter Maydell | |
| 2011-03-10 | Add patterns for saturating 8 and 16 bit add/sub | Peter Maydell | |
| 2011-02-21 | Add VRECPE and VRSQRTE patterns | Peter Maydell | |
| 2011-02-15 | Add patterns for Neon shifts, zip and unzip. | Peter Maydell | |
| 2011-02-11 | Document the .risu format in the README | Peter Maydell | |
| Document the .risu file format in the README, rather than in three duplicate comments in risugen, arm.risu and thumb.risu. | |||
| 2011-02-11 | Add ARM patterns for long polynomial multiply (VMULL.P8) | Peter Maydell | |
| 2011-02-09 | Add a VQMOVN pattern. | Peter Maydell | |
| 2011-02-09 | Add patterns for VSHLL. | Peter Maydell | |
| 2011-02-09 | Add some commented out untested patterns for narrowing shifts. | Peter Maydell | |
| 2011-02-09 | Uncomment half-precision patterns as they are now tested. | Peter Maydell | |
| 2011-02-07 | Add patterns for ARM vsli, vsri and vsra. | Peter Maydell | |
| 2011-02-07 | Fix lack of bracketing on some constraints in arm.risu. | Peter Maydell | |
| 2011-02-03 | Add patterns for ARM encoding hint and preload space. | Peter Maydell | |
| 2011-01-27 | Add ARM patterns for VQ(R)DMULH | Peter Maydell | |
| 2011-01-27 | ARM: add Neon saturating add/sub patterns | Peter Maydell | |
| 2011-01-19 | Add ARM patterns: VMLAL, VMLSL, VQDMLAL, VQDMLSL, VMULL, VQDMULL | Peter Maydell | |
| Add patterns for VMLAL, VMLSL, VQDMLAL, VQDMLSL, VMULL, VQDMULL (both scalar and non-scalar forms) | |||
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index : pmaydell/risu.git | |
| risu: random instruction sequence tester for userspace |
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